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Macros</h2></td></tr>
<tr class="memitem:ga5e55891344ab473841b6eefc2bda35a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga5e55891344ab473841b6eefc2bda35a2">XSpi_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;XSpi_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:ga5e55891344ab473841b6eefc2bda35a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read from the specified Spi device register.  <a href="group__spi__v4__1.html#ga5e55891344ab473841b6eefc2bda35a2">More...</a><br /></td></tr>
<tr class="separator:ga5e55891344ab473841b6eefc2bda35a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga32e741800118678aa060ef2a13661e31"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga32e741800118678aa060ef2a13661e31">XSpi_WriteReg</a>(BaseAddress,  RegOffset,  RegisterValue)&#160;&#160;&#160;XSpi_Out32((BaseAddress) + (RegOffset), (RegisterValue))</td></tr>
<tr class="memdesc:ga32e741800118678aa060ef2a13661e31"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write to the specified Spi device register.  <a href="group__spi__v4__1.html#ga32e741800118678aa060ef2a13661e31">More...</a><br /></td></tr>
<tr class="separator:ga32e741800118678aa060ef2a13661e31"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga48fdfb116f37c7f14403bed57b556c4c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga48fdfb116f37c7f14403bed57b556c4c">XSP_SRR_RESET_MASK</a>&#160;&#160;&#160;0x0000000A</td></tr>
<tr class="memdesc:ga48fdfb116f37c7f14403bed57b556c4c"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPI Software Reset Register (SRR) mask.  <a href="group__spi__v4__1.html#ga48fdfb116f37c7f14403bed57b556c4c">More...</a><br /></td></tr>
<tr class="separator:ga48fdfb116f37c7f14403bed57b556c4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>XSPI register offsets</p>
<p>Register offsets for the <a class="el" href="struct_x_spi.html" title="The XSpi driver instance data. ">XSpi</a> device. </p>
</div></td></tr>
<tr class="memitem:ga3a66b8345fe53a19c2da1a8162dc366d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga3a66b8345fe53a19c2da1a8162dc366d">XSP_DGIER_OFFSET</a>&#160;&#160;&#160;0x1C</td></tr>
<tr class="memdesc:ga3a66b8345fe53a19c2da1a8162dc366d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Intr Enable Reg.  <a href="group__spi__v4__1.html#ga3a66b8345fe53a19c2da1a8162dc366d">More...</a><br /></td></tr>
<tr class="separator:ga3a66b8345fe53a19c2da1a8162dc366d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2bc4dc18547b8bdd05c5eb2b73c9ff7d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga2bc4dc18547b8bdd05c5eb2b73c9ff7d">XSP_IISR_OFFSET</a>&#160;&#160;&#160;0x20</td></tr>
<tr class="memdesc:ga2bc4dc18547b8bdd05c5eb2b73c9ff7d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt status Reg.  <a href="group__spi__v4__1.html#ga2bc4dc18547b8bdd05c5eb2b73c9ff7d">More...</a><br /></td></tr>
<tr class="separator:ga2bc4dc18547b8bdd05c5eb2b73c9ff7d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gace876b867131a62e5407d440c73d6693"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gace876b867131a62e5407d440c73d6693">XSP_IIER_OFFSET</a>&#160;&#160;&#160;0x28</td></tr>
<tr class="memdesc:gace876b867131a62e5407d440c73d6693"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enable Reg.  <a href="group__spi__v4__1.html#gace876b867131a62e5407d440c73d6693">More...</a><br /></td></tr>
<tr class="separator:gace876b867131a62e5407d440c73d6693"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa82028ecd15bcffd8ab361c0c523a7a9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gaa82028ecd15bcffd8ab361c0c523a7a9">XSP_SRR_OFFSET</a>&#160;&#160;&#160;0x40</td></tr>
<tr class="memdesc:gaa82028ecd15bcffd8ab361c0c523a7a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Software Reset register.  <a href="group__spi__v4__1.html#gaa82028ecd15bcffd8ab361c0c523a7a9">More...</a><br /></td></tr>
<tr class="separator:gaa82028ecd15bcffd8ab361c0c523a7a9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3a63aa98328d40e3221901143e128da1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga3a63aa98328d40e3221901143e128da1">XSP_CR_OFFSET</a>&#160;&#160;&#160;0x60</td></tr>
<tr class="memdesc:ga3a63aa98328d40e3221901143e128da1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control register.  <a href="group__spi__v4__1.html#ga3a63aa98328d40e3221901143e128da1">More...</a><br /></td></tr>
<tr class="separator:ga3a63aa98328d40e3221901143e128da1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae4915bf726554a2abf5922129f88542b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gae4915bf726554a2abf5922129f88542b">XSP_SR_OFFSET</a>&#160;&#160;&#160;0x64</td></tr>
<tr class="memdesc:gae4915bf726554a2abf5922129f88542b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status Register.  <a href="group__spi__v4__1.html#gae4915bf726554a2abf5922129f88542b">More...</a><br /></td></tr>
<tr class="separator:gae4915bf726554a2abf5922129f88542b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02929309d91a658ac28746aee48d0c04"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga02929309d91a658ac28746aee48d0c04">XSP_DTR_OFFSET</a>&#160;&#160;&#160;0x68</td></tr>
<tr class="memdesc:ga02929309d91a658ac28746aee48d0c04"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data transmit.  <a href="group__spi__v4__1.html#ga02929309d91a658ac28746aee48d0c04">More...</a><br /></td></tr>
<tr class="separator:ga02929309d91a658ac28746aee48d0c04"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga078846fea7538049312959d15b44a9dd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga078846fea7538049312959d15b44a9dd">XSP_DRR_OFFSET</a>&#160;&#160;&#160;0x6C</td></tr>
<tr class="memdesc:ga078846fea7538049312959d15b44a9dd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data receive.  <a href="group__spi__v4__1.html#ga078846fea7538049312959d15b44a9dd">More...</a><br /></td></tr>
<tr class="separator:ga078846fea7538049312959d15b44a9dd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga34c2ab4de85d2a3a5659e5446235942c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga34c2ab4de85d2a3a5659e5446235942c">XSP_SSR_OFFSET</a>&#160;&#160;&#160;0x70</td></tr>
<tr class="memdesc:ga34c2ab4de85d2a3a5659e5446235942c"><td class="mdescLeft">&#160;</td><td class="mdescRight">32-bit slave select  <a href="group__spi__v4__1.html#ga34c2ab4de85d2a3a5659e5446235942c">More...</a><br /></td></tr>
<tr class="separator:ga34c2ab4de85d2a3a5659e5446235942c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf06c80c0767e40c86b2e3fc18457d680"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gaf06c80c0767e40c86b2e3fc18457d680">XSP_TFO_OFFSET</a>&#160;&#160;&#160;0x74</td></tr>
<tr class="memdesc:gaf06c80c0767e40c86b2e3fc18457d680"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx FIFO occupancy.  <a href="group__spi__v4__1.html#gaf06c80c0767e40c86b2e3fc18457d680">More...</a><br /></td></tr>
<tr class="separator:gaf06c80c0767e40c86b2e3fc18457d680"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4e120064bd2a34a145d54608ccef4107"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga4e120064bd2a34a145d54608ccef4107">XSP_RFO_OFFSET</a>&#160;&#160;&#160;0x78</td></tr>
<tr class="memdesc:ga4e120064bd2a34a145d54608ccef4107"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx FIFO occupancy.  <a href="group__spi__v4__1.html#ga4e120064bd2a34a145d54608ccef4107">More...</a><br /></td></tr>
<tr class="separator:ga4e120064bd2a34a145d54608ccef4107"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Global Interrupt Enable Register (GIER) mask(s)</div></td></tr>
<tr class="memitem:ga492a1b3f6bb367fbb9e88b514722b13c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga492a1b3f6bb367fbb9e88b514722b13c">XSP_GINTR_ENABLE_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:ga492a1b3f6bb367fbb9e88b514722b13c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global interrupt enable.  <a href="group__spi__v4__1.html#ga492a1b3f6bb367fbb9e88b514722b13c">More...</a><br /></td></tr>
<tr class="separator:ga492a1b3f6bb367fbb9e88b514722b13c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">SPI Device Interrupt Status/Enable Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p><b> Interrupt Status Register (IPISR) </b></p>
<p>This register holds the interrupt status flags for the Spi device.</p>
<p><b> Interrupt Enable Register (IPIER) </b></p>
<p>This register is used to enable interrupt sources for the Spi device. Writing a '1' to a bit in this register enables the corresponding Interrupt. Writing a '0' to a bit in this register disables the corresponding Interrupt.</p>
<p>ISR/IER registers have the same bit definitions and are only defined once. </p>
</div></td></tr>
<tr class="memitem:gae1c1ffa1846ef388873861bf017aec7a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gae1c1ffa1846ef388873861bf017aec7a">XSP_INTR_MODE_FAULT_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gae1c1ffa1846ef388873861bf017aec7a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode fault error.  <a href="group__spi__v4__1.html#gae1c1ffa1846ef388873861bf017aec7a">More...</a><br /></td></tr>
<tr class="separator:gae1c1ffa1846ef388873861bf017aec7a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad8f8c52684a188989df6463cfa44e90f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gad8f8c52684a188989df6463cfa44e90f">XSP_INTR_SLAVE_MODE_FAULT_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gad8f8c52684a188989df6463cfa44e90f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Selected as slave while disabled.  <a href="group__spi__v4__1.html#gad8f8c52684a188989df6463cfa44e90f">More...</a><br /></td></tr>
<tr class="separator:gad8f8c52684a188989df6463cfa44e90f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa8ec3c2cf6ffb5824012e63935fe94cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gaa8ec3c2cf6ffb5824012e63935fe94cf">XSP_INTR_TX_EMPTY_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gaa8ec3c2cf6ffb5824012e63935fe94cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">DTR/TxFIFO is empty.  <a href="group__spi__v4__1.html#gaa8ec3c2cf6ffb5824012e63935fe94cf">More...</a><br /></td></tr>
<tr class="separator:gaa8ec3c2cf6ffb5824012e63935fe94cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9a7a08185e86401169c2f810642f08ec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga9a7a08185e86401169c2f810642f08ec">XSP_INTR_TX_UNDERRUN_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga9a7a08185e86401169c2f810642f08ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">DTR/TxFIFO underrun.  <a href="group__spi__v4__1.html#ga9a7a08185e86401169c2f810642f08ec">More...</a><br /></td></tr>
<tr class="separator:ga9a7a08185e86401169c2f810642f08ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga154fc50d2dfa52ec08b03a202484f8b0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga154fc50d2dfa52ec08b03a202484f8b0">XSP_INTR_RX_FULL_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga154fc50d2dfa52ec08b03a202484f8b0"><td class="mdescLeft">&#160;</td><td class="mdescRight">DRR/RxFIFO is full.  <a href="group__spi__v4__1.html#ga154fc50d2dfa52ec08b03a202484f8b0">More...</a><br /></td></tr>
<tr class="separator:ga154fc50d2dfa52ec08b03a202484f8b0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae4313597b27da75830905e5510d6c7ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gae4313597b27da75830905e5510d6c7ba">XSP_INTR_RX_OVERRUN_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gae4313597b27da75830905e5510d6c7ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">DRR/RxFIFO overrun.  <a href="group__spi__v4__1.html#gae4313597b27da75830905e5510d6c7ba">More...</a><br /></td></tr>
<tr class="separator:gae4313597b27da75830905e5510d6c7ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga17b6c5a44bb267e1d71293adfc225cc4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga17b6c5a44bb267e1d71293adfc225cc4">XSP_INTR_TX_HALF_EMPTY_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga17b6c5a44bb267e1d71293adfc225cc4"><td class="mdescLeft">&#160;</td><td class="mdescRight">TxFIFO is half empty.  <a href="group__spi__v4__1.html#ga17b6c5a44bb267e1d71293adfc225cc4">More...</a><br /></td></tr>
<tr class="separator:ga17b6c5a44bb267e1d71293adfc225cc4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaac9322f55b43ad653b2dd630df73ac6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gaaac9322f55b43ad653b2dd630df73ac6">XSP_INTR_SLAVE_MODE_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:gaaac9322f55b43ad653b2dd630df73ac6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave select mode.  <a href="group__spi__v4__1.html#gaaac9322f55b43ad653b2dd630df73ac6">More...</a><br /></td></tr>
<tr class="separator:gaaac9322f55b43ad653b2dd630df73ac6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf4fa2bf85266797c3806a885144f0a67"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gaf4fa2bf85266797c3806a885144f0a67">XSP_INTR_RX_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:gaf4fa2bf85266797c3806a885144f0a67"><td class="mdescLeft">&#160;</td><td class="mdescRight">RxFIFO not empty.  <a href="group__spi__v4__1.html#gaf4fa2bf85266797c3806a885144f0a67">More...</a><br /></td></tr>
<tr class="separator:gaf4fa2bf85266797c3806a885144f0a67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4411b96eab10163334a172e8c7fff16e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga4411b96eab10163334a172e8c7fff16e">XSP_INTR_CPOL_CPHA_ERR_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:ga4411b96eab10163334a172e8c7fff16e"><td class="mdescLeft">&#160;</td><td class="mdescRight">The following bits are available only in axi_qspi Interrupt Status and Interrupt Enable registers.  <a href="group__spi__v4__1.html#ga4411b96eab10163334a172e8c7fff16e">More...</a><br /></td></tr>
<tr class="separator:ga4411b96eab10163334a172e8c7fff16e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02214d826551eaa28053bbe31961d7d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga02214d826551eaa28053bbe31961d7d8">XSP_INTR_SLAVE_MODE_ERR_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:ga02214d826551eaa28053bbe31961d7d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave mode error.  <a href="group__spi__v4__1.html#ga02214d826551eaa28053bbe31961d7d8">More...</a><br /></td></tr>
<tr class="separator:ga02214d826551eaa28053bbe31961d7d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadab0807b07832514f750466433646109"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gadab0807b07832514f750466433646109">XSP_INTR_MSB_ERR_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:gadab0807b07832514f750466433646109"><td class="mdescLeft">&#160;</td><td class="mdescRight">MSB Error.  <a href="group__spi__v4__1.html#gadab0807b07832514f750466433646109">More...</a><br /></td></tr>
<tr class="separator:gadab0807b07832514f750466433646109"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab391120a5227047af0568687b386bee9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gab391120a5227047af0568687b386bee9">XSP_INTR_LOOP_BACK_ERR_MASK</a>&#160;&#160;&#160;0x00001000</td></tr>
<tr class="memdesc:gab391120a5227047af0568687b386bee9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Loop back error.  <a href="group__spi__v4__1.html#gab391120a5227047af0568687b386bee9">More...</a><br /></td></tr>
<tr class="separator:gab391120a5227047af0568687b386bee9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga78efad507778d0d5fe669486d4ac8558"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga78efad507778d0d5fe669486d4ac8558">XSP_INTR_CMD_ERR_MASK</a>&#160;&#160;&#160;0x00002000</td></tr>
<tr class="memdesc:ga78efad507778d0d5fe669486d4ac8558"><td class="mdescLeft">&#160;</td><td class="mdescRight">'Invalid cmd' error  <a href="group__spi__v4__1.html#ga78efad507778d0d5fe669486d4ac8558">More...</a><br /></td></tr>
<tr class="separator:ga78efad507778d0d5fe669486d4ac8558"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf2c321040c3a93daa19aa3fcc77c86e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gaf2c321040c3a93daa19aa3fcc77c86e8">XSP_INTR_ALL</a></td></tr>
<tr class="memdesc:gaf2c321040c3a93daa19aa3fcc77c86e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask for all the interrupts in the IP Interrupt Registers.  <a href="group__spi__v4__1.html#gaf2c321040c3a93daa19aa3fcc77c86e8">More...</a><br /></td></tr>
<tr class="separator:gaf2c321040c3a93daa19aa3fcc77c86e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga99707579afa353242a403526ddebcb6d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga99707579afa353242a403526ddebcb6d">XSP_INTR_DFT_MASK</a></td></tr>
<tr class="memdesc:ga99707579afa353242a403526ddebcb6d"><td class="mdescLeft">&#160;</td><td class="mdescRight">The interrupts we want at startup.  <a href="group__spi__v4__1.html#ga99707579afa353242a403526ddebcb6d">More...</a><br /></td></tr>
<tr class="separator:ga99707579afa353242a403526ddebcb6d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">SPI Control Register (CR) masks</div></td></tr>
<tr class="memitem:ga6a060df48208ca7e56572762233ceadb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga6a060df48208ca7e56572762233ceadb">XSP_CR_LOOPBACK_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga6a060df48208ca7e56572762233ceadb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Local loopback mode.  <a href="group__spi__v4__1.html#ga6a060df48208ca7e56572762233ceadb">More...</a><br /></td></tr>
<tr class="separator:ga6a060df48208ca7e56572762233ceadb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1c10904273bbeb8fb8fc502c5cc9cdf6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga1c10904273bbeb8fb8fc502c5cc9cdf6">XSP_CR_ENABLE_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga1c10904273bbeb8fb8fc502c5cc9cdf6"><td class="mdescLeft">&#160;</td><td class="mdescRight">System enable.  <a href="group__spi__v4__1.html#ga1c10904273bbeb8fb8fc502c5cc9cdf6">More...</a><br /></td></tr>
<tr class="separator:ga1c10904273bbeb8fb8fc502c5cc9cdf6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga25aabcaa1db090de7cf4aaf3cb05ea6b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga25aabcaa1db090de7cf4aaf3cb05ea6b">XSP_CR_MASTER_MODE_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga25aabcaa1db090de7cf4aaf3cb05ea6b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable master mode.  <a href="group__spi__v4__1.html#ga25aabcaa1db090de7cf4aaf3cb05ea6b">More...</a><br /></td></tr>
<tr class="separator:ga25aabcaa1db090de7cf4aaf3cb05ea6b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga522187d5fb382dfa512f02be7fe0068b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga522187d5fb382dfa512f02be7fe0068b">XSP_CR_CLK_POLARITY_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga522187d5fb382dfa512f02be7fe0068b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock polarity high or low.  <a href="group__spi__v4__1.html#ga522187d5fb382dfa512f02be7fe0068b">More...</a><br /></td></tr>
<tr class="separator:ga522187d5fb382dfa512f02be7fe0068b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga87d555bd447b511847632a2fe19b8b04"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga87d555bd447b511847632a2fe19b8b04">XSP_CR_CLK_PHASE_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga87d555bd447b511847632a2fe19b8b04"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock phase 0 or 1.  <a href="group__spi__v4__1.html#ga87d555bd447b511847632a2fe19b8b04">More...</a><br /></td></tr>
<tr class="separator:ga87d555bd447b511847632a2fe19b8b04"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab7796329c185988f906256394bc9372f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gab7796329c185988f906256394bc9372f">XSP_CR_TXFIFO_RESET_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gab7796329c185988f906256394bc9372f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset transmit FIFO.  <a href="group__spi__v4__1.html#gab7796329c185988f906256394bc9372f">More...</a><br /></td></tr>
<tr class="separator:gab7796329c185988f906256394bc9372f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5b5e5793f12d648025e58f716862bb3e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga5b5e5793f12d648025e58f716862bb3e">XSP_CR_RXFIFO_RESET_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga5b5e5793f12d648025e58f716862bb3e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset receive FIFO.  <a href="group__spi__v4__1.html#ga5b5e5793f12d648025e58f716862bb3e">More...</a><br /></td></tr>
<tr class="separator:ga5b5e5793f12d648025e58f716862bb3e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga68b5a025e603ab87d7987e2220507e6c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga68b5a025e603ab87d7987e2220507e6c">XSP_CR_MANUAL_SS_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:ga68b5a025e603ab87d7987e2220507e6c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Manual slave select assert.  <a href="group__spi__v4__1.html#ga68b5a025e603ab87d7987e2220507e6c">More...</a><br /></td></tr>
<tr class="separator:ga68b5a025e603ab87d7987e2220507e6c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2d045067441152dbf5729d4dce64032b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga2d045067441152dbf5729d4dce64032b">XSP_CR_TRANS_INHIBIT_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga2d045067441152dbf5729d4dce64032b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master transaction inhibit.  <a href="group__spi__v4__1.html#ga2d045067441152dbf5729d4dce64032b">More...</a><br /></td></tr>
<tr class="separator:ga2d045067441152dbf5729d4dce64032b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9af1189aa0cf7ba871c47201d0721683"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga9af1189aa0cf7ba871c47201d0721683">XSP_CR_LSB_MSB_FIRST_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:ga9af1189aa0cf7ba871c47201d0721683"><td class="mdescLeft">&#160;</td><td class="mdescRight">LSB/MSB first data format select.  <a href="group__spi__v4__1.html#ga9af1189aa0cf7ba871c47201d0721683">More...</a><br /></td></tr>
<tr class="separator:ga9af1189aa0cf7ba871c47201d0721683"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">SPI Control Register (CR) masks for XIP Mode</div></td></tr>
<tr class="memitem:ga8b1a0aa05d64095856c125f38acb55bf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga8b1a0aa05d64095856c125f38acb55bf">XSP_CR_XIP_CLK_PHASE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga8b1a0aa05d64095856c125f38acb55bf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock phase 0 or 1.  <a href="group__spi__v4__1.html#ga8b1a0aa05d64095856c125f38acb55bf">More...</a><br /></td></tr>
<tr class="separator:ga8b1a0aa05d64095856c125f38acb55bf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9e07ebf282cf0dee542bd5a3b9f41641"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga9e07ebf282cf0dee542bd5a3b9f41641">XSP_CR_XIP_CLK_POLARITY_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga9e07ebf282cf0dee542bd5a3b9f41641"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock polarity high or low.  <a href="group__spi__v4__1.html#ga9e07ebf282cf0dee542bd5a3b9f41641">More...</a><br /></td></tr>
<tr class="separator:ga9e07ebf282cf0dee542bd5a3b9f41641"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Status Register (SR) masks</div></td></tr>
<tr class="memitem:ga25dfccf25bae24caa237ec3b75825438"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga25dfccf25bae24caa237ec3b75825438">XSP_SR_RX_EMPTY_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga25dfccf25bae24caa237ec3b75825438"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive Reg/FIFO is empty.  <a href="group__spi__v4__1.html#ga25dfccf25bae24caa237ec3b75825438">More...</a><br /></td></tr>
<tr class="separator:ga25dfccf25bae24caa237ec3b75825438"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3c8077ca32c93bbd7ee52a6a9ab33e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gaf3c8077ca32c93bbd7ee52a6a9ab33e1">XSP_SR_RX_FULL_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gaf3c8077ca32c93bbd7ee52a6a9ab33e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive Reg/FIFO is full.  <a href="group__spi__v4__1.html#gaf3c8077ca32c93bbd7ee52a6a9ab33e1">More...</a><br /></td></tr>
<tr class="separator:gaf3c8077ca32c93bbd7ee52a6a9ab33e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaa5946629075b285ce0c4b90a87f4fec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gaaa5946629075b285ce0c4b90a87f4fec">XSP_SR_TX_EMPTY_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gaaa5946629075b285ce0c4b90a87f4fec"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit Reg/FIFO is empty.  <a href="group__spi__v4__1.html#gaaa5946629075b285ce0c4b90a87f4fec">More...</a><br /></td></tr>
<tr class="separator:gaaa5946629075b285ce0c4b90a87f4fec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2666d211089b037853ee6d1f80130ae7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga2666d211089b037853ee6d1f80130ae7">XSP_SR_TX_FULL_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga2666d211089b037853ee6d1f80130ae7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit Reg/FIFO is full.  <a href="group__spi__v4__1.html#ga2666d211089b037853ee6d1f80130ae7">More...</a><br /></td></tr>
<tr class="separator:ga2666d211089b037853ee6d1f80130ae7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5ab61ff6d56a82f18573abe33958b27e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga5ab61ff6d56a82f18573abe33958b27e">XSP_SR_MODE_FAULT_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga5ab61ff6d56a82f18573abe33958b27e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode fault error.  <a href="group__spi__v4__1.html#ga5ab61ff6d56a82f18573abe33958b27e">More...</a><br /></td></tr>
<tr class="separator:ga5ab61ff6d56a82f18573abe33958b27e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf6ed84865dc8c3e3d2cb7835b4007159"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gaf6ed84865dc8c3e3d2cb7835b4007159">XSP_SR_SLAVE_MODE_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gaf6ed84865dc8c3e3d2cb7835b4007159"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave mode select.  <a href="group__spi__v4__1.html#gaf6ed84865dc8c3e3d2cb7835b4007159">More...</a><br /></td></tr>
<tr class="separator:gaf6ed84865dc8c3e3d2cb7835b4007159"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2aeb63586150ee640f93d38bf611e583"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga2aeb63586150ee640f93d38bf611e583">XSP_SR_CPOL_CPHA_ERR_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga2aeb63586150ee640f93d38bf611e583"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPOL/CPHA error.  <a href="group__spi__v4__1.html#ga2aeb63586150ee640f93d38bf611e583">More...</a><br /></td></tr>
<tr class="separator:ga2aeb63586150ee640f93d38bf611e583"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d08afc5481f3746c444b682aa7b1de1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga5d08afc5481f3746c444b682aa7b1de1">XSP_SR_SLAVE_MODE_ERR_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:ga5d08afc5481f3746c444b682aa7b1de1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave mode error.  <a href="group__spi__v4__1.html#ga5d08afc5481f3746c444b682aa7b1de1">More...</a><br /></td></tr>
<tr class="separator:ga5d08afc5481f3746c444b682aa7b1de1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3da5f67ae5a952127614beec3b1556eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga3da5f67ae5a952127614beec3b1556eb">XSP_SR_MSB_ERR_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga3da5f67ae5a952127614beec3b1556eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">MSB Error.  <a href="group__spi__v4__1.html#ga3da5f67ae5a952127614beec3b1556eb">More...</a><br /></td></tr>
<tr class="separator:ga3da5f67ae5a952127614beec3b1556eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5affffc9ae318a0d1187235d4df45d3b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga5affffc9ae318a0d1187235d4df45d3b">XSP_SR_LOOP_BACK_ERR_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:ga5affffc9ae318a0d1187235d4df45d3b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Loop back error.  <a href="group__spi__v4__1.html#ga5affffc9ae318a0d1187235d4df45d3b">More...</a><br /></td></tr>
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<tr class="memitem:ga05d94bc7a9205d80dd3024783f0cde82"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga05d94bc7a9205d80dd3024783f0cde82">XSP_SR_CMD_ERR_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:ga05d94bc7a9205d80dd3024783f0cde82"><td class="mdescLeft">&#160;</td><td class="mdescRight">'Invalid cmd' error  <a href="group__spi__v4__1.html#ga05d94bc7a9205d80dd3024783f0cde82">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Status Register (SR) masks for XIP Mode</div></td></tr>
<tr class="memitem:ga03c4fc141be312d0f92ea72ba89cac12"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga03c4fc141be312d0f92ea72ba89cac12">XSP_SR_XIP_RX_EMPTY_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga03c4fc141be312d0f92ea72ba89cac12"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive Reg/FIFO is empty.  <a href="group__spi__v4__1.html#ga03c4fc141be312d0f92ea72ba89cac12">More...</a><br /></td></tr>
<tr class="separator:ga03c4fc141be312d0f92ea72ba89cac12"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9cbb3b1a05ab5e38813e5ba66f63b751"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga9cbb3b1a05ab5e38813e5ba66f63b751">XSP_SR_XIP_RX_FULL_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga9cbb3b1a05ab5e38813e5ba66f63b751"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive Reg/FIFO is full.  <a href="group__spi__v4__1.html#ga9cbb3b1a05ab5e38813e5ba66f63b751">More...</a><br /></td></tr>
<tr class="separator:ga9cbb3b1a05ab5e38813e5ba66f63b751"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga82d05e2bede7d12b74e6994d8bfaaab8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga82d05e2bede7d12b74e6994d8bfaaab8">XSP_SR_XIP_MASTER_MODF_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga82d05e2bede7d12b74e6994d8bfaaab8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive Reg/FIFO is full.  <a href="group__spi__v4__1.html#ga82d05e2bede7d12b74e6994d8bfaaab8">More...</a><br /></td></tr>
<tr class="separator:ga82d05e2bede7d12b74e6994d8bfaaab8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga894c3b5bd8cd47deb1aa84303733d97c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga894c3b5bd8cd47deb1aa84303733d97c">XSP_SR_XIP_CPHPL_ERROR_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga894c3b5bd8cd47deb1aa84303733d97c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock Phase,Clock Polarity Error.  <a href="group__spi__v4__1.html#ga894c3b5bd8cd47deb1aa84303733d97c">More...</a><br /></td></tr>
<tr class="separator:ga894c3b5bd8cd47deb1aa84303733d97c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7cabf5324694e10915a45cabf9872a28"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga7cabf5324694e10915a45cabf9872a28">XSP_SR_XIP_AXI_ERROR_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga7cabf5324694e10915a45cabf9872a28"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXI Transaction Error.  <a href="group__spi__v4__1.html#ga7cabf5324694e10915a45cabf9872a28">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">SPI Transmit FIFO Occupancy (TFO) mask</div></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSP_TFO_MASK</b>&#160;&#160;&#160;0x0000001F</td></tr>
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<tr><td colspan="2"><div class="groupHeader">SPI Receive FIFO Occupancy (RFO) mask</div></td></tr>
<tr class="memitem:gaac20d42377c8de368527a37e39121666"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSP_RFO_MASK</b>&#160;&#160;&#160;0x0000001F</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Data Width Definitions</div></td></tr>
<tr class="memitem:ga7c85879d831cff400f3919c3283089dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#ga7c85879d831cff400f3919c3283089dc">XSP_DATAWIDTH_BYTE</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ga7c85879d831cff400f3919c3283089dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx/Rx Reg is Byte Wide.  <a href="group__spi__v4__1.html#ga7c85879d831cff400f3919c3283089dc">More...</a><br /></td></tr>
<tr class="separator:ga7c85879d831cff400f3919c3283089dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabd886cf61eba8074e747ebec9df258dd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gabd886cf61eba8074e747ebec9df258dd">XSP_DATAWIDTH_HALF_WORD</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:gabd886cf61eba8074e747ebec9df258dd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx/Rx Reg is Half Word (16 bit) Wide.  <a href="group__spi__v4__1.html#gabd886cf61eba8074e747ebec9df258dd">More...</a><br /></td></tr>
<tr class="separator:gabd886cf61eba8074e747ebec9df258dd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gace732a635dfcd0b6258449945444b31c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__v4__1.html#gace732a635dfcd0b6258449945444b31c">XSP_DATAWIDTH_WORD</a>&#160;&#160;&#160;32</td></tr>
<tr class="memdesc:gace732a635dfcd0b6258449945444b31c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx/Rx Reg is Word (32 bit) Wide.  <a href="group__spi__v4__1.html#gace732a635dfcd0b6258449945444b31c">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">SPI Modes</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The following constants define the modes in which qxi_qspi operates. </p>
</div></td></tr>
<tr class="memitem:gadb9526c0fe208894f41ac9a75a4ae33b"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSP_STANDARD_MODE</b>&#160;&#160;&#160;0</td></tr>
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<tr class="memitem:ga2ffc4a0643a5b408ddc5865cd932679b"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSP_DUAL_MODE</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:ga65123199589f10eb456ffc73a0473d10"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSP_QUAD_MODE</b>&#160;&#160;&#160;2</td></tr>
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